An Exclusive Switching Performance: Power Factor Correction in Hybrid Modular Multilevel Converter

  • Mr. Balasaheb J. Pawar Assistant Professor, N.D.M.V.P.S’s, C.O.E., Nashik, Maharashtra, India

Abstract

This article is devoted to the multi-level inverters and in particular to the switching and power factor correction (PFC) of hybrid modular multilevel converter (HMMC).The HMMC is built up by individually controllable sub-modules (SMs). Therefore the converter can act as a controllable voltage source converter with a large number of discrete voltage steps. Various pulse-width modulation (PWM) switching processswhich are based on a single reference waveform are developed / proposed for the MMC. Active filtering of electric power consumes now develop a mature technology for harmonic mitigation and PFC in ac power networks with nonlinear loads. This paper presents an exclusive switching process which is also helpful to maintain the power factor (PF) of HMMC.


How to cite this article:
Pawar B.J, Gond V.J. An Exclusive Switching Performance: Power Factor Correction in Hybrid Modular Multilevel Converter. J Adv Res Microelec VLSI 2020; 2(1): 4-9.

References

[1]. C. Davidson, D. Trainer, Innovative Concepts for Hybrid Multi-Level Converters for HVDC Power Transmission, in: 9th IET International Conference on AC and DC Power Transmission (ACDC 2010), 2010.
[2]. B. Jacobson, P. Karlsson, G. Asplund, L. Harnefors, T. Jonsson, VSC-HVDC Transmission with Cascaded Two-Level Converters, in: CIGR´E B4-110, 2010.
[3]. R. Marquardt, “Modular multilevel converter: An universal concept for HVDC-networks and extended DC-bus-applications,” in Proc. Int. Power Electron. Conf., Jun. 2010, pp. 502–507.
[4]. G. Konstantinou and V. Agelidis, “Performance evaluation of half-bridge cascaded multilevel converters operated with multicarrier sinusoidal PWM processs,” in Proc. IEEE Conf. Ind. Electron. Appl., 2009, pp. 3399–3404.
[5]. A. Hassanpoor, S. Norrga, H. Nee, and L. Angquist, “Evaluation of different carrier-based PWM methods for modular multilevel converters for HVDC application,” in Proc. Conf. IEEE Ind. Electron. Soc., 2012, pp. 388–393.
[6]. D.-W. Kang, W.-K. Lee, and D.-S. Hyun, “Carrier-Rotation strategy for voltage balancing in flying capacitor multilevel inverter,” IEE Proc.— Electric Power Appl., vol. 151, no. 2, pp. 239–248, 2004.
[7]. B.-S. Jin, W. kyo Lee, T.-J. Kim, D.-W. Kang, and D.-S. Hyun, “A study on the multi-carrier PWM methods for voltage balancing of flying capacitor in the flying capacitor multi-level inverter,” in Proc. Conf. IEEE Ind. Electron. Soc., 2005, p. 6.
[8]. M. Saeedifard and R. Iravani, “Dynamic performance of a modular multilevel back-to-back HVDC system,” IEEE Trans. Power Del., vol. 25, no. 4, pp. 2903–2912, Oct. 2010.
[9]. J. Mei, K. Shen, B. Xiao, L. Tolbert, and J. Zheng, “A new selective loop bias mapping phase disposition PWM with dynamic voltagebalance capability for modular multilevel converter,” IEEE Trans. Ind. Electron., vol. 61, no. 2, pp. 798–807, Feb. 2014.
[10]. M. Hagiwara and H. Akagi, “Control and experiment of pulse width modulated modular multilevel converters,” IEEE Trans. Power Electron., vol. 24, no. 7, pp. 1737–1746, Jul. 2009.
[11]. G. Konstantinou, M. Ciobotaru, and V. Agelidis, “Selective harmonic elimination pulse-width modulation of modular multilevel converters,” IET Power Electron., vol. 6, no. 1, pp. 96–107, 2013.
[12]. Q. Tu and Z. Xu, “Impact of sampling frequency on harmonic distortion for modular multilevel converter,” IEEE Trans. Power Del., vol. 26, no. 1, pp. 298–306, Jan. 2011.
[13]. J. Huber and A. Korn, “Optimized pulse pattern modulation for modular multilevel converter high-speed drive,” in Proc. Int. Power Electron. Motion Control Conf., 2012, pp. LS1a-1.4-1–LS1a-1.4-7.
Published
2021-10-01
How to Cite
PAWAR, Mr. Balasaheb J.. An Exclusive Switching Performance: Power Factor Correction in Hybrid Modular Multilevel Converter. Journal of Advanced Research in Microelectronics and VLSI, [S.l.], v. 2, n. 1, p. 4-9, oct. 2021. Available at: <http://thejournalshouse.com/index.php/ADR-Microelectronics-VLSI/article/view/390>. Date accessed: 20 may 2024.