A SYSTEMATIC REVIEW ON HYPERSCALE IMPLEMENTATION FOR TOP LEVEL DESIGN Author

Abstract

With the growth in the VLSI industry , Complexity of design has increased   both with respect to   size and technology . Memory consumed  and runtime impact is a major problem for the design especially when it comes to timing closure for the large chips . There have been many techniques to avoid such problems . This paper explains the various approaches in brief and explains in detail the hyperscale implementation  approach . It also compares the HS implementation with flat run through a case study of GPU  and  bolster the adoption of the technique , addressing all the pros and cons.