Exploring Circuit Optimization in VLSI: A Comprehensive Review
Abstract
Transistors can be operated more simply and can be put into devices as switches thanks to digital circuits. The introduction of vacuum tubes had
a significant impact on the electronics industry, but there were some challenges, like high power and 100 anode tension. The development of the transistor in the microelectronics sector used only a few watts. It ended up serving as the basis for low-energy appliances. Power per unit area has increased due to the integration of several functionalities into a single chip and improvements in circuit performance, which have also increased the need for cooling and heat removal systems. Low
power is their major concern in the VLSI context.
References
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[2] A. Peiravi and M. Asyaei, “Current-comparison-based Domino: New Low-leakage High-speed Domino Circuit for Wide Fan-in Gates,” IEEE Transactions on Very Large Scale Integration Systems, vol. 21, no. 5, pp. 934–943, 2013.
[3] Ambily Babu (2014) “Power Optimization Techniques at Circuit and Device Level in Digital CMOS VLSI – A Review” International Journal of Engineering Research & Technology (IJERT) IJERT ISSN: 2278-0181 IJERTV3IS110434 www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) Vol. 3 Issue 11,
November-2014
[4] Anuj and Divya Khanna (2014) “A Literature Review on Design Strategies and Methodologies of Low Power VLSI Circuits” IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 2, Ver. IV (Mar-Apr. 2014), PP 17- 21 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org
[5] Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky and Alexander Fish, “Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design”, Integration, the VLSI journal, Vol. 47, 62-70, 2014.
[6] B. R. Zeydel, D. Baran, and V. G. Oklobdzija, “Energy-efficient Design Methodologies: High-performance VLSI Adders,” IEEE Journal of Solid-State Circuits, vol. 45, no. 6, pp. 1220–1233, 2010.
[7] B. T. Geetha, B. Padmavathi and V. Perumal (2017) “Design methodologies and circuit optimization techniques for low power CMOS VLSI design” DOI: 10.1109/ICPCSI.2017.8392016 https://ieeexplore.ieee.org/document/8392016
[8] C. A. Coello, “A short tutorial on evolutionary multiobjective optimization,” in Proc. 1st Int. Conf. Evolutionary Multi- Criterion Optimization, 2011, pp. 21–40.
[9] C. Efstathiou, Z. Owda, and Y. Tsiatouhas, “New High-Speed Multioutput Carry Look-Ahead Adders,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 10, pp. 667–671, 2013.
[10] Coello, Carlos A., Christiansen, Alan D. & Hernández Aguirre, “Using Genetic Algorithms to Design Combinational Logic Circuits.” ANNIE'. Intelligent Engineering through Artificial Neural Networks, Volume 6. Smart Engineering Systems: Neural Networks, Fuzzy Logic and Evolutionary Programming. Edited by Cihan H. Dagli, Metin Akay, C. L. Philip Chen, Benito R. Fernandez and Joydeep Ghosh. pp. 391-396. November, 2016.
[11] D. A. Patterson and J. L. Hennessy, Computer Organization and Design: The Hardware/Software Interface. Newnes, 2013.
[12] Dennard RH, Cai J, Kumar A. A Perspective on today’s scaling challenges and possible future directions: in Handbook of Thin Film Deposition (Fourth Edition).2018:3-18.
[13] Duan, C., Calle, V.H.C. and Khatri, S.P. (2009), “Efficient on-chip crosstalk avoidance codec design”, Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17 No. 4, pp. 551-560.
[14] F. J. Rodriguez, C. Garcia-Martinez, and M. Lozano, “Hybrid Meta-heuristics Based on Evolutionary Algorithms and Simulated Annealing: Taxonomy, Comparison, and Synergy Test,” IEEE Transactions on Evolutionary Computation, vol. 16, no. 6, pp. 787–800, 2012.
[15] G. Martin, B. Bailey, and A. Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology. Morgan Kaufmann, 2010.
[16] G. Palumbo, M. Pennisi, and M. Alioto, “A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 59, no. 10, pp. 2292–2300, 2012.
[17] Gary K. Yeap, “Practical Low Power Digital VLSI Design” , Kluwer Academic, Publishers, 2008.
[18] H. Tennakoon and C. Sechen. Gate Sizing using Lagrangian Relaxation Combined with a Fast Gradient based Preprocessing Step. In International Conference on Computer Aided Design, pages 395–402, 2012.
[19] H. Tennakoon and C. Sechen. Gate Sizing using Lagrangian Relaxation Combined with a Fast Gradient based Preprocessing Step. In International Conference on Computer Aided Design, pages 395–402, 2012.
[20] J. Kathuria, M. Ayoubkhan, and A. Noor, “A Review of Clock Gating Techniques,” MIT International Journal of Electronics and Communication Engineering, vol. 1, no. 2, pp. 106–114, 2011.
[21] J. Lu, W.-K. Chow, and C.-W. Sham, “Fast-Power and Slew-Aware Gated Clock Tree Synthesis,” IEEE Transactions on Very Large Scale Integration Systems, vol. 20, no. 11, pp. 2094–2103, 2012.
[22] J. Wu, Y.-L. Shen, K. Reinhardt, H. Szu, and B. Dong, “A Nanotechnology Enhancement to Moore’s Law,” Applied Computational Intelligence and Soft Computing, vol. 2, pp. 2–15, 2013.
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[24] J.P. Fishburn and A.E. Dunlop. TILOS A Posynomial Programming Approach to Transistor Sizing. In International Conference on Computer Aided Design, pages 326–336, 2015.
[25] K. Darbinyan, G. Harutyunyan, S. Shoukourian, V. Vardanian, and Y. Zorian, “A robust solution for embedded memory test and repair,” in Proc. IEEE Asian Test Symp., Nov. 2012, pp. 461–462.
[26] Kamal K Mehta, “A Review on Strategies and Methodologies of Dynamic Power Reduction on Low Power System Design” in ijcsc Volume 7, No 1, 2016.
[27] Kapil Mangla and Shashank Saxena, “Analysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design”, International Journal of Engineering and Technical Research (IJETR), Vol. 3, No-5, May 2015.
[28] Krishna Kumar S., S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay,” Customizing Pattern Set for Test Power Reduction via Improved X-identification and Reordering,” ISLPED’10, August 18–20, 2010, Austin, Texas, USA,Pp.No.177-182.
[29] Krishna Kumar S., S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay,” Particle Swarm Optimization based Vector Reordering for Low Power Testing,” 2010 Second International conference on Computing, Communication and Networking Technologies
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[32] L. Li and K. Choi, “Activity-driven Optimised Bus-specific-clock-gating for Ultra-lowpower Smart Space Applications,” IET communications, vol. 5, no. 17, pp. 2501–2508, 2011.
[33] L. P. P. P. van Ginneken, “Buffer placement in distributed RC-tree network for minimal Elmore delay,” in Proc. IEEE Int.
Symp. Circuits Syst., 1990, pp. 865–868
[34] L. Raja, K. Thanushkodi, and T. Hemalatha, “Comparitive Analysis of Various Low Power Clock Gating Design for ALU,” in Proceedings of IEEE International Conference on Electronics and Communication Systems, 2014, pp. 1–5.
[35] L.P.P.P van Ginneken. Buffer placement in distributed rc-tree networks for minimal elmore delay. In International Symposium on Circuits and Systems, pages 190–197, 2010.
[36] Lee and Touba, (2007) “Low Power Test Data Compression Based on LFSR Reseeding” https://www.researchgate.net/publication/4099092_Low_power_test_data_compression_based_on_LFSR_reseeding
[37] Lin, T.W., Tu, S.W. and Jou, J.Y. (2007), “On chip bus encoding for power minimization under delay constraint”, IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Ambassador Hotel, Hsinchu, 25-27 April, available at: http://vlsidat.itri.org. tw
[38] M Berkelaar and J. Jess. Gate Sizing in MOS Digital Circuits with Linear Programming. In European Design Automation Conference, pages 217–221, 2013.
[39] M. Alioto, G. Palumbo, and M. Pennisi, “Understanding the Effect of Process Variations on the Delay of Static and Domino Logic,” IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 5, pp. 697–710, 2010.
[40] M. Ehrgott and X. Gandibleux. Multiple Criteria Optimization. State of the Art Annotated Bibliographic Surveys. Kluwer, 2012.
[41] M. Hu, T. Wu, and J. D. Weir, “An Adaptive Particle Swarm Optimization with Multiple Adaptive Methods,” IEEE Transactions on Evolutionary Computation, vol. 17, no. 5, pp. 705–720, 2013.
Published
2023-10-16
How to Cite
PANDEY, Rishab.
Exploring Circuit Optimization in VLSI: A Comprehensive Review.
Journal of Advanced Research in Microelectronics and VLSI, [S.l.], v. 6, n. 1, p. 5-12, oct. 2023.
Available at: <http://thejournalshouse.com/index.php/ADR-Microelectronics-VLSI/article/view/867>. Date accessed: 19 may 2024.
Section
Research Article
