Powering the Future: Emerging Paradigms in Low-Power VLSI Design
Abstract
This study surveys the recent trends in the innovations and advancements in the field of low power VLSI Design. Although Low Power is a wellestablished field, it has seen several advancements, including adiabatic logic. Other advancements include transistor sizing, process shrinkage, voltage scaling, clock gating, etc. The purpose of this paper is to discuss recent developments in low power design.
References
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in low-voltage processors. Proceedings of IEEE Conference on Custom Integrated Circuits.
15. Goyal C., & sood, I. Low power data bus encoding & decoding schemes.
16. Yang, J., Gupta, R., & Zhang, C. (July 2004). Frequent value encoding for low power data buses. ACM Transactions
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17. Gojman, B. (August 8, 2004). Adiabatic Logic.
18. Samanta, S. (December 2009). Adiabatic computing: a contemporary review. Proceedings of International Conference
on Computers and Devices for Communication (pp. 1-4).
19. Younis, S., & Knight, T. (June 1994). Asymptotically zero energy computing using split level charge recovery logic.
Technical Report AITR-1500, MIT AI Laboratory.
20. Teichmann, P. (2012). Adiabatic Logic. Springer Series in Advanced Microelectronics 34.
21. Moon Y., & Jeong, D. K. (April 1996). An Efficient charge recovery logic circuit. IEEE Journal of Solid-State Circuits,
31(4).
22. Mishra, A., Jaiswal, A., & Niketa, A. K. (May 2014). Design and analysis of conventional cmos and energy efficient
adiabatic logic for low power VLSI application. International Journal of Engineering and Advanced Technology
(IJEAT), 3(12).
23. Jaggi, T., Kumar, R., & Sharma, N. (May 2013). Power efficient positive feedback adiabatic logic. Proceedings of
National Conference on Signal Processing and Communication Technology.
24. Sowjanya, M., & Malik, S. A. (Jul-Aug 2013). Efficiency of adiabatic logic for low-power VLSI using cascaded ECRL
and PFAL inverter. International Journal of Engineering Research and Applications, 3(4), 1277-1280.
25. Maurya, A. K., & Kumar, G. (2011). Energy efficient adiabatic logic for low power vlsi applications. Proceedings of
International Conference on Communication Systems And Network Technologies (pp. 460-464).
26. Bhaaskaran, V. S., & Raina, J. P. (August 2012). Pre-Resolve and sense adiabatic logic for 100 KHz to 500 MHz
Frequency Classes. Journal of Circuits, Systems and Computers, 21(5).
Addison–Wesley.
2. Roy, K., et al. (February 2003). Leakage current mechanisms and leakage reduction techniques in deep submicrometer
CMOS circuits. Proceedings of the IEEE,
3. Synopsys, Inc. introduction page. Retrieved from the website: http://www.synopsys.com/lowpower/Documents
4. Altera Corporation. (May 2008). AN 531: Reducing power with hardware accelerators. Ver. 1.0, Application Note 531.
5. Power management. Retrieved from the ARM. Mbed website: http://Mbed.Org/Cookbook/PowerManagement
6. Kathuria, J., Ayoubkhan, M., & Noor, A. (Aug. 2011). A Review of clock gating techniques. MIT International Journal
of Electronics and Communication Engineering, 1(2), 106-114.
7. Retrieved from the website: http://www.synopsys.com/advanced-low-power-techniques.aspx Tawfik, S. A. (May
2009). Low power and high speed multi threshold voltage interface circuits. IEEETransactions on Very Large Scale
Integration (VLSI) Systems, 17(5).
8. Dokić, B. L. (2013). A Review on energy efficient CMOS digital logic. ETASR - Engineering, Technology & Applied
Science Research, 3, 552-561.
9. Gayasen, A., Lee, K., Vijaykrishnan, N., Kandemir, M., Irwin, J., & Tuan, T. (July 2004). A Dual-VDD low power FPGA
architecture.
10. Usami, K., & Horowitz, (1995). M. Clustered voltage scaling technique for low power design. Proceedings of the
1995 International Symposium.
11. Pillai, P., & Shin, K. G. (Dec. 2001). Real-Time dynamic voltage scaling for low-power embedded operating systems.
Proceedings of the Eighteenth ACM Symposium on Operating Systems Principles.
12. Texas Instruments. Adaptive voltage scaling technology up to 60% energy savings for digital core operation.
13. Hartman, M. (March 2008). Processor energy savings through adaptive voltage scaling. Issue of Portable Design.
14. Nose, K., Hirabayashi, M., Kawaguchi, H., Lee S., & Sakurai, T. (2001). VTH-hopping scheme for 82% power saving
in low-voltage processors. Proceedings of IEEE Conference on Custom Integrated Circuits.
15. Goyal C., & sood, I. Low power data bus encoding & decoding schemes.
16. Yang, J., Gupta, R., & Zhang, C. (July 2004). Frequent value encoding for low power data buses. ACM Transactions
on Design Automation of Electronic Systems, 9(3), 354–384.
17. Gojman, B. (August 8, 2004). Adiabatic Logic.
18. Samanta, S. (December 2009). Adiabatic computing: a contemporary review. Proceedings of International Conference
on Computers and Devices for Communication (pp. 1-4).
19. Younis, S., & Knight, T. (June 1994). Asymptotically zero energy computing using split level charge recovery logic.
Technical Report AITR-1500, MIT AI Laboratory.
20. Teichmann, P. (2012). Adiabatic Logic. Springer Series in Advanced Microelectronics 34.
21. Moon Y., & Jeong, D. K. (April 1996). An Efficient charge recovery logic circuit. IEEE Journal of Solid-State Circuits,
31(4).
22. Mishra, A., Jaiswal, A., & Niketa, A. K. (May 2014). Design and analysis of conventional cmos and energy efficient
adiabatic logic for low power VLSI application. International Journal of Engineering and Advanced Technology
(IJEAT), 3(12).
23. Jaggi, T., Kumar, R., & Sharma, N. (May 2013). Power efficient positive feedback adiabatic logic. Proceedings of
National Conference on Signal Processing and Communication Technology.
24. Sowjanya, M., & Malik, S. A. (Jul-Aug 2013). Efficiency of adiabatic logic for low-power VLSI using cascaded ECRL
and PFAL inverter. International Journal of Engineering Research and Applications, 3(4), 1277-1280.
25. Maurya, A. K., & Kumar, G. (2011). Energy efficient adiabatic logic for low power vlsi applications. Proceedings of
International Conference on Communication Systems And Network Technologies (pp. 460-464).
26. Bhaaskaran, V. S., & Raina, J. P. (August 2012). Pre-Resolve and sense adiabatic logic for 100 KHz to 500 MHz
Frequency Classes. Journal of Circuits, Systems and Computers, 21(5).
Published
2023-10-16
How to Cite
PANDEY, Rishab.
Powering the Future: Emerging Paradigms in Low-Power VLSI Design.
Journal of Advanced Research in Microelectronics and VLSI, [S.l.], v. 6, n. 1, p. 17-30, oct. 2023.
Available at: <http://thejournalshouse.com/index.php/ADR-Microelectronics-VLSI/article/view/869>. Date accessed: 19 may 2024.
Section
Research Article
