A Novel VLSI Design of Efficient Approximate Booth Multiplier
Abstract
This research proposes an approximation multiplier for error-resistant applications that is fast and energy efficient at the same time. Variable probability components are introduced into the multiplier’s partial products in this novel design technique for 16-bit approximation of multiplier. The difficulty of approximation is influenced by the possibility of accumulating changing partial products. XILINX synthesis findings show that the suggested multiplier outperforms an exact multiplier in terms of performance. Existing approximation multipliers don’t have as much precision as these.
How to cite this article:
Dova M, Sandi AM. A Novel VLSI Design of Efficient Approximate Booth Multiplier. J Adv Res Microelec VLSI 2021; 4(2): 1-6.
References
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11. Venkatesan R, Agarwal A, Roy K et al. MACACO: Modeling and analysis of circuits for approximate computing. Proc. IEEE/ ACM Int. Conf. Comput.-Aided Design (ICCAD). 2011; 667-673.
12. Liang J, Han J, Lombardi F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans Comput 2013; 63(9): 1760-1771.
13. Suman S. Image enhancement using geometric mean filter and gamma correction for WCE iamges. Proc. 21st Int. Conf., Neural Inf. Process. (ICONIP). 2014; 276-283.
2. King EJ, Swartzlander EE. Data-dependent truncation scheme for parallel multipliers. Proc. 31st Asilomar Conf. Signals, Circuits Syst. 1998; 1178-1182.
3. Cho KJ, Lee KC, Chung JG et al. Design of low-error fixed-width modified booth multiplier. IEEE Trans Very Large Scale Integr (VLSI) Syst 2004; 12(5): 522-531.
4. Mahdiani HR, Ahmadi A, Fakhraie SM et al. Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. IEEE Trans Circuits Syst 2010; 57(4): 850-862.
5. Momeni A, Han J, Montuschi P et al. Design and analysis of approximate compressors for multiplication. IEEE Trans Comput 2015; 64(4): 984-994.
6. Narayanamoorthy S, Moghaddam HA, Liu Z et al. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Trans Very Large Scale Integr (VLSI) Syst 2015; 23(6): 1180-1184.
7. Zervakis G, Tsoumanis K, Xydis S et al. Design-efficient approximate multiplication circuits through partial product perforation. IEEE Trans Very Large Scale Integr (VLSI) Syst 2016; 24(10): 3105-3117.
8. Kulkarni P, Gupta P, Ercegovac MD. Trading accuracy for power in a multiplier architecture. J Low Power Electron 2011; 7(4): 490-501.
9. Lin CH, Lin C. High accuracy approximate multiplier with error correction. Proc. IEEE 31st Int. Conf. Comput. Design. 2013; 33-38.
10. Liu C, Han J, Lombardi F. A low-power, high-performance approximate multiplier with configurable partial error recovery. Proc. Conf. Exhibit. 2014; 1-4.
11. Venkatesan R, Agarwal A, Roy K et al. MACACO: Modeling and analysis of circuits for approximate computing. Proc. IEEE/ ACM Int. Conf. Comput.-Aided Design (ICCAD). 2011; 667-673.
12. Liang J, Han J, Lombardi F. New metrics for the reliability of approximate and probabilistic adders. IEEE Trans Comput 2013; 63(9): 1760-1771.
13. Suman S. Image enhancement using geometric mean filter and gamma correction for WCE iamges. Proc. 21st Int. Conf., Neural Inf. Process. (ICONIP). 2014; 276-283.
Published
2022-04-01
How to Cite
SANDI, Anuradha M; DOVA, Murali.
A Novel VLSI Design of Efficient Approximate Booth Multiplier.
Journal of Advanced Research in Microelectronics and VLSI, [S.l.], v. 4, n. 2, p. 1-6, apr. 2022.
Available at: <http://thejournalshouse.com/index.php/ADR-Microelectronics-VLSI/article/view/551>. Date accessed: 20 may 2024.
Section
Review Article
