Efficient Design Strategies for Low Power and Area in VLSI CircuitsEfficient Design Strategies for Low Power and Area in VLSI Circuits

  • Bhagya Shri Electrical and Electronics Engineering, Amrita Vishwa Vidyapeetham, Coimbatore.

Abstract

Leakage power, which accounts for an ever-increasing fraction of chip overall power consumption in deep submicron technologies, is crucial for a low power design. When designing CMOS VLSI circuits, power dissipation is a crucial factor. In battery-powered applications, high power consumption reduces battery life and has an impact on packing, cooling, dependability. We provide a method for constructing CMOS gates dubbed LCPMOS that considerably reduces leakage current without raising dynamic power dissipation. Leakage power is essential for a low power design since it represents an ever-increasing portion of the
overall chip power consumption in deep submicron technologies. Power dissipation is an important consideration while building CMOS VLSI circuits. High power consumption affects reliability, cooling, packaging, battery life in applications that use batteries. We provide the LCPMOS approach, which significantly lowers leakage current without increasing dynamic power dissipation, for building CMOS gates. A single additional leakage control transistor, driven by the output from the pull up and pull down networks, is used in LCPMOS, a technique to address the leakage issue in CMOS circuits. It is placed in a path from the pull down
network to ground and provides the additional resistance, reducing the leakage current in the path from supply to ground.The primary advantage over other systems is that the LCPMOS technology doesn’t need any additional control and monitoring circuitry, hence reducing the active state power consumption and constricting the active state area. Along with this, another benefit of the LCPMOS approach is that it decreases leakage power to a level of 91.54%, which is more effective than other leakage power reduction techniques in terms of area and power dissipation.

References

1. P. Verma, R. A. Mishra, “Leakage power and delay analysis of LECTOR based CMOS circuits”, Int’l conf. on computer & communication technology ICCCT 2011.
2. H. Narender and R. Nagarajan, “LECTOR: A technique for leakage reduction in CMOS circuits”, IEEE trans. on VLSI systems, vol. 12, no. 2, Feb. 2004.
3. L. Wei, Z. Chen, M. Johnson, K. Roy, “Design and optmization of low voltage high performance dual threshold CMOS circuits,” in Proc. 35th DAC, 1998, pp. 489–492.
4. John F. Wakerly, “Digital Design- Principles and Practices”, fourth edition.
5. M. C. Johnson, D. Somasekhar, L. Y. Chiou, K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,” IEEE Trans. VLSI Syst., vol. 10, pp. 1–5, Feb. 2002.
6. bthreshold leakage reduction in CMOS digital circuits,” in Proc. 13th NASA VLSI Symp.,June 2007.
7. Q. Wang and S. Vrudhula, “Static power optimization of deep sub- micron CMOS circuits for dual VT technology,” in Proc. ICCAD, Apr. 1998, pp. 490–496.
8. M. D. Powell, S. H. Yang, B. Falsafi, K. Roy, T. N. Vijaykumar, “Gated-Vdd: A ciruit technique to reduce leakage in deep submicron cache memories,” in Proc. IEEE ISLPED, 2000, pp. 90-95.
9. S. H. Kim and V. J. Mooney, “Sleepy Keeper: a new approach to low-leakage power VLSI design,” IFIP, pp.
10. 367-372, 2006.
11. J. C. Park, “Sleepy Stack: A new approach to Low Power VLSI logic and memory,” Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Published
2023-10-16
How to Cite
SHRI, Bhagya. Efficient Design Strategies for Low Power and Area in VLSI CircuitsEfficient Design Strategies for Low Power and Area in VLSI Circuits. Journal of Advanced Research in Microelectronics and VLSI, [S.l.], v. 6, n. 1, p. 13-16, oct. 2023. Available at: <http://thejournalshouse.com/index.php/ADR-Microelectronics-VLSI/article/view/868>. Date accessed: 19 may 2024.