Surveying Low Power VLSI Design Techniques: A Comprehensive Review

Priya Garg

Priya Garg Department of Electrical Engineering, Rajkiya Engineering College, Sonbhadra.

Abstract

In the electronics industry of today, low power has become a major theme. For the design of VLSI chips, power dissipation has taken on equal importance to performance and area. The main issues below 100nm due to increased complexity are lowering power usage and overall power management on chip. Due to the requirement to lower package costs and increase battery life, power optimisation is crucial for many systems. In low power VLSI designs, leakage current also has a significant impact on power management. An growing portion of integrated circuits’ overall power dissipation is being accounted for by leakage current. This paper discusses numerous power management techniques, methodologies, and tactics for low power circuits and systems. Future challenges that must be met to designs low power high performance circuits are also discussed.

References

1. Michael Keating, David Flynn, Robert Aitken, Ala Gibsons and Kaijian Shi, “Low Power Methodology Manual for
System on Chip Design”, Springer Publications, New York, 2007. Creating Low-Power Digital Integrated Circuits
The Implementation Phase, Cadence, 2007.
2. Liu, Weidong, Xiaodong Jin, Xuemei Xi, James Chen, Min-Chie Jeng, Zhihong Liu, Yuhua Cheng, Kai Chen, Mansun
Chan, Kelvin Hui, Jianhui Huang, Robert Tu, Ping K Ko, and Chenming Hu, BSIM3v3.3 MOSFET Model User’s Manual,
Department of Electrical Engineering and Computer Sciences, University of California-Berkeley, 2005.
3. Glasser, Lance A, and Daniel W Dobberpuhl, TheDesign and Analysis of VLSI Circuits, Addison-Wesley Publishing
Co, 1985.
4. Shekar Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, July/August 1999, pg 23.
5. T. Inukai, et.al, “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage- Free Giga-
Scale Integration,” Proc. CICC 2000, pp.409- 412.
6. F.Hamzaoglu and M. Stan, “Circuit-Level Techniques to Control Gate Leakage for sub 100nm CMOS,” Proc. ISLPED,
pp. 60-63, Aug. 2002.
7. Y. Yeo, et.al, “Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric,”
IEEE Electron Devices Letters, vol.21, no.11, pp. 540-542, Nov.2000.
8. S. Mutoh, et.al, “1-V Power Supply High-Speed Digital Circuit Technology with Multi-Threshold Voltage CMOS,”IEEE
Journal of Solid State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
9. M.Alidina, j. Monterio, S. Devadas, A.Ghosh and M. Papaefthymiou. “Precomputation –based Sequential logic
optimization for low power” In Proceedings of the 1994 International Workshop on Low Power Design, pages 57-
62, April 1994.
10. Anand Iyer, “Demystify power gating and stop leakage cold”, Cadence Design Systems, Inc.
11. De-Shiuan Chiou, Shih-Hsin Chen, Chingwei Yeh, “Timing driven power gating”, Proceedings of the 43rd annual
conference on Design automation,ACM Special Interest Group on Design Automation, pp.121 - 124, 2006.
12. B.Perman, “Design technologies for VLSI design”, encyclopedia of computer science,1995.
13. Mentor Graphics, “Low power physical design with Olympus SOC”, Place and route white paper, March 27, 2009.
14. Rahul. M.Rao, Jeffery L.Burns, Richard B.Brown, “Circuit Techniques for gate and subthreshold leakage minimization
in future CMOS technologies” Proc. ISLPED, pp70-73, 2002.
15. J.kao, Siva Narendra, Ananta Chandra Kasan, “Subthresh leakage modeling and reduction technique”, 2002.
16. Prasad Subramanian, “Power management for optimal power design”, ESILICON, Corp.2010.