A Review on Low Power SRAM
Abstract
In any digital system, memory is main part and no digital system can be completed without memories. Now a days Embedded system and compact size devices are developed. So low power consumption is an important issue in system design. In VLSI design, the main issues are increased packing density, scaling in silicon technology and optimizing the speed. Due to these, there is increased power dissipation in system. So, there is a need to design a low power SRAM to increase run time with small size and high performance. In this paper basic operation of SRAM and different techniques to reduce total power dissipation are discussed.
How to cite this article:
Patil M. A Review on Low Power SRAM. J Adv Res Appl Arti Intel Neural Netw 2019; 2(2): 9-12.
References
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[10] Navid Azizi, Farid N. Najm and Andreas Moshovos, “ Low-Leakage Asymmetric-Cell SRAM”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 11, No. 4, August 2003.
[2] Kanika, Pawan Kumar Dahiya, “A Review on Low Power SRAM”, International Journal on Recent Trends in Engineering and Research, Volume 3, Issue 5, May 2017, pp. 366-370.
[3] Shin-Pao Cheng and Shi-Yu Haung, “A low power SRAM design with quiet-bitline architecture”, Memory Technology, Design and Testing, 2005. MTDT 2005.2005 IEEE International Workshop.
[4] G. Kalaiarasi, V. Indhumaraghathavalli , A. Manoranjitham, P. Narmatha, “A Novel Architecture of SRAM Cell Using Single Bit-Line”, International Journal of Innovative Research in Computer and Communication Engineering, Vol. 2, Special Issue 1, March 2014.
[5] Song li, Zhiting Lin, Jiubai Zhang, Yuchun Peng and Xiulong Wu, “A Novel 8T SRAM Cell with Improved Read and Write Margins”, International Conference on Applied Science and Engineering Innovation 2015.
[6] Nahid Rahman and B. P. Singh, “Design and Verification of Low Power SRAM using 8T SRAM Cell Approach” International Journal of Computer Applications (0975-8887) Vol. 67, No. 18, April 2013.
[7] Jinmo Kwon, Ik Joon Chang, Insoo Lee, Heemin Park and Jongson Park, “Heterogenous SRAM Cell Sizing for Low-Power H.264 Applications” IEEE Transactions on Circuits and Systems-I: Regular Papers, Volume 59, No. 10, POctober 2012.
[8] E. Seevinck, F. List and J. Lohstroh , “Static Noise Margin Analysis of MOS SRAM cells”, IEEE J. Solid State Circuits, Vol. SC-22, No. 5, pp. 748-754, Oct. 1987.
[9] Benton H. Calhoun, Anantha P. Chadrakasan, “Static Noise Margin Variation for Sub-threshold SRAM in 65nm CMOS”, IEEE Journal of Solid State Circuits, Vol. 41, No. 7, July 2006, pp. 1673-1679.
[10] Navid Azizi, Farid N. Najm and Andreas Moshovos, “ Low-Leakage Asymmetric-Cell SRAM”, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 11, No. 4, August 2003.
Published
2021-09-30
How to Cite
PATIL, Manasi.
A Review on Low Power SRAM.
Journal of Advanced Research in Applied Artificial Intelligence and Neural Network, [S.l.], v. 3, n. 2, p. 15-18, sep. 2021.
Available at: <http://thejournalshouse.com/index.php/neural-network-intelligence-adr/article/view/371>. Date accessed: 22 dec. 2024.
