Low Power Techniques in VLSI

  • Amrita Pahadia Research Scholar, Bhabha University, Bhopal, Madhya Pradesh, India.
  • Soni Changlani Professor and Head, Department of Electronics and Communication, Lakshmi Narain College of Technology, Bhopal, Madhya Pradesh, India.


Low power is extremely crucial in today’s VLSI technology, as seen by the current trends in the industry. In low-power VLSI designs, assessment techniques and extension circuits are used to improve performance. Power dissipation is primarily considered in terms of performance and area. Because of improved quality, reduced power consumption and power management on the chip remain the most difficult tasks to overcome even at 100nm and beyond. When it comes to power optimization, lowering the cost of the package and increasing battery life are both critical considerations. Leakage current is critical in power management because low power consumption is a significant negative in high-performance digital and microchip systems, which are becoming increasingly common. The leakage current of integrated circuits is a significant contributor to the total power dissipation of the device. It is only important for a winning chip to have low power consumption and accurate power dissipation calculations. A wide range of issues are discussed in this work, ranging from device or method level to formula level, including future concerns that must be addressed in the design and application of low power circuits.

How to cite this article:
Pahadia A, Changlani S. Low Power Techniques in VLSI. J Adv Res Electro Engi Tech 2021; 8(3&4): 1-7.


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How to Cite
PAHADIA, Amrita; CHANGLANI, Soni. Low Power Techniques in VLSI. Journal of Advanced Research in Electronics Engineering and Technology, [S.l.], v. 8, n. 3&4, p. 1-7, nov. 2021. ISSN 2456-1428. Available at: <https://thejournalshouse.com/index.php/electronics-engg-technology-adr/article/view/519>. Date accessed: 17 aug. 2022.