Design and Optimisation of a Robust D-Flip Flop in Quantum-dot Cellular Automata Technology using QCA Designer

Abstract

The continued scaling of complementary metal-oxide-semiconductor (CMOS) technology faces inherent physical and energetic limits, driving the necessity for alternative computing paradigms. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology offering ultra-low power dissipation, extremely high integration density, and potential operational frequencies in the terahertz range, relying on coherent electronic charge configuration (polarization) rather than current flow. This study details the design, optimisation, and verification of a fundamental sequential memory element—the D-Flip Flop (D-FF)—implemented entirely within the QCA framework. A novel and area-efficient master-slave D-FF architecture, essential for synchronous data storage, was developed. The design prioritises minimal cell count, reduced latency, and robust operation under QCA’s critical four-phase clocking scheme. Using the QCA Designer simulation tool, the proposed layout was rigorously analysed for functional completeness, timing reliability, and performance metrics, including cell area utilisation and clock delay. The resultant D-FF demonstrates stable memory functionality, successfully capturing and holding input data (D) synchronised to the clock edge (CLK), validating the feasibility of complex sequential circuits in emerging QCA architectures.